This application claims the benefit of priority under 35 U.S.C. xc2xa7119 of Japanese Patent Application No. H11-302056, filed on Oct. 25, 1999, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
This invention relates to a line interface integrated circuit and a packet switch, and more particularly, to a line interface circuit capable of efficiently inserting or extracting packets, and a packet switch using such a line interface integrated circuit.
2. Description of the Related Background Art
There is an ATM (asynchronous transfer mode) communication network as one of currently widespread communication networks of fixed length packets. ATM networks are used to exchange not only ordinary data cells but also non-data cells for maintenance and management of the ATM networks.
For example, ATM networks can use OAM (operation and maintenance) cells for the purpose of maintenance of the networks. Furthermore, RM (resource management) cells can be also used for the purpose of efficiently using network resources of the ATM networks.
In order to operate and manage an ATM network by using those OAM cells and RM cells, communication terminals or ATM switches are required to insert OAM cells and RM cells into a flow of ordinary data cells or extract OAM cells and RM cells from the flow of ordinary cells. A configuration of an ATM switch of this type is shown in FIG. 9.
As shown in FIG. 9, the ATM switch has physical layer controllers 110(1) through 110(N), line interfaces 112(1) through 112(N), routing switch 114, line interfaces 116(1) through 116(N), and physical layer controllers 118(1) through 118(N).
The line interfaces 112(1) through 112(N) and the physical layer controllers 110(1) through 110(N) are associated with respective input ports. That is, in the example of FIG. 9, there are N input ports. The line interfaces 116(1) through 116(N) and the physical layer controllers 118(1) through 118(N) are associated with respective output ports. That is, in the example of FIG. 9, there are N output ports.
The physical layer controllers 110(1) to 110(N) are connected to physical layers, respectively, and supplied with frame-formatted transmission data from the physical layers. As to these frame-formatted transmission data inputted into physical layer controllers 110(1) to 110(N), ATM cells are extracted from each frame-formatted transmission data and outputted to the line interfaces 112(1) to 112(N). That is, a plurality of ATM cells are stored in one frame.
The line interfaces 112(1) to 112(N) connected between the physical layer controllers 110(1) to 110(N) and the routing switch 114 function to add information required for routing the ATM cells in the routing switch 114 to ATM cells, rewrite headers of ATM cells, and so on. The line interfaces 112(1) to 112(N) also function to temporarily store ATM cells to be outputted to the routing switch 114 and output them to the routing switch 114, depending upon the processing status of the routing switch 114. The line interfaces 112(1) to 112(N) are concerned in processing ATM cells from the physical layer controllers 110(1) to 110(N) toward the routing switch 114, and the part of the ATM switch where these ATM cells enter into the routing switch 114 is hereinafter called the ingress side.
ATM cells outputted from the line interfaces 112(1) to 112(N) are inputted to the routing switch 114. By switching function of the routing switch 114 based on header information of the ATM cells, these ATM cells are outputted to a corresponding one of line interfaces 116(1) to 116(N), respectively.
The line interfaces 116(1) to 116(N) temporarily store ATM cells inputted from the routing switch 114 and sequentially output them to the physical layer controllers 118(1) to 118(N) as soon as the output port is unoccupied. The line interfaces 116(1) to 116(N) are concerned in processing ATM cells from the routing switch 114 toward the physical layer controllers 118(1) to 118(N), and the part of the ATM switch where these ATM cells are outputted from the routing switch 114 is hereinafter called the egress side.
Based on ATM cells inputted into the physical layer controllers 118(1) through 118(N), frame-formatted transmission data are generated in the physical layer controllers 118(1) to 118(N), and the transmission data is outputted from a physical layer.
In case of an ATM switch having configuration as shown in FIG. 9, insertion and extraction of the OAM cells or the RM cells are often conducted in the ingress-side line interfaces 112(1) to 112(N) and/or egress-side line interfaces 116(1) to 116(N). Configuration of line interfaces 112(1) to 112(N) having such functions of inserting and extracting of the OAM cells and the RM cells is shown in FIG. 10. FIG. 10 illustrates configuration of an ingress-side line interface 112(1) as an example.
With reference to FIG. 10, explanation is made below about the process of ordinary data cells passing through the conventional line interface 112(1).
ATM cells inputted from the physical layer controller 110(1) are classified in a physical layer interface 130. Based on the classification, class information CI is notified from the physical layer interface 130 to a scheduler 132. The class information CI indicates an identification number of a queue formed in a cell buffer 134. The scheduler 132 manages the queues, each of which corresponds to the class.
The scheduler 132 in receipt of the class information CI outputs a write request W to write ATM cells to the cell buffer 134. Responsively, ATM cells are stored in the cell buffer 134 via a cell storage controller 131. The scheduler 132 writes data of a single ATM cell in the cell buffer 134, and thereafter adds one entry in a class queue the ATM cell belongs to, and increases the length of the queue by one. Herein below, let it called xe2x80x9cenqueuexe2x80x9d to write data of an ATM cell in the cell buffer 134 and increase the length of a queue the ATM cell belongs to.
The scheduler 132 selects any queue or queues equal to or longer than 1 from a plurality of queues provided for individual classes, and selects only one to be outputted with the highest priority. The scheduler 132 extracts the forefront one entry of the selected queue, and a data read request to read data of the ATM cell that entry belongs to. Herein below, let it called xe2x80x9cdequeuexe2x80x9d to read out cell data from the cell buffer 134 and decrease the length of the queue the ATM cell belongs to.
Next referring to FIG. 10, explanation is made about operations in the line interface 112(1) for extracting an OAM cell and RM cell, and operations therein for inserting an OAM cell and RM cell.
The physical layer interface 130 manages information for individual lines, such as line qualities (class information CI), cell passing frequencies, etc. When the physical layer interface 130 decides on the basis of contents of input cells and line information that an ATM cell inputted is addressed to the host CPU, it writes the data of the ATM cell in a FIFO memory 136 prepared separately, instead of the cell buffer 134.
The FIFO memory 136 is capable of storing a plurality of ATM cell data. The host CPU 150 connected to the line interface 112(1) has the function of sequentially reading out ATM cell data from the FIFO memory 136 into temporary RAM 138, the function of delivering information obtained therefrom to application software, and other functions.
On the other hand, for inserting an OAM cell or RM cell, the host CPU 150 first writes data of the ATM cell to be inserted in the temporary RAM 138, and requests a cell insertion controller 140 to next insert the ATM cell. The cell insertion controller 140 outputs ATM cells stored in the temporary RAM 138 through a selector 142 to a switch interface 144 when, for example, there are no cell to be dequeued.
However, the line interface 112(1) explained above with reference to FIG. 10 involves the following problem. That is, since it was undefined how often OAM cells or RM cells arrive, the FIFO memory 136 was required to have an amply large capacity with a margin taking the processing speed of the host CPU 150 into consideration. However, even if using a FIFO memory 136 having an ample margin, when OAM cells or RM cells addressed to the host CPU 150 arrived successively, they might exceed the capacity of the FIFO memory 136.
Additionally, even when the scheduler 132 tried to output ATM cells, which are ordinary data cells, from the switch interface 144 so as to maintain a predetermined line quality, there was the possibility that OAM cells or RM cells inserted from the host CPU 150 invited a delay of ATM cells, which are ordinary data cells. Moreover, since the selector 142 had to be controlled to minimize such a delay of data cells, the control mechanism of the cell insertion controller 140 was indispensably complicated.
It is therefore an object of the invention to provide a line interface not requiring particular attention to capacity of a FIFO memory, and an ATM switch as a kind of packet switches using such line interfaces.
In other words, it is the object of the invention to provide a line interface integrated circuit capable of inserting non-data cells for maintenance and management purposes into a flow of ordinary data ATM cells without disordering the flow of the ATM cells and extracting non-data cells from a flow of ATM cells, and an ATM switch as one of packet switches using such line interface integrated circuit.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a line interface integrated circuit having an input-side interface supplied with packets and an output-side interface outputting the packets, comprising:
a first storage device configured to temporarily store packets toward CPU and be accessed by the CPU when necessary; and
a scheduler configured to classify packets outputted from the input-side interface at least into a first queue for accumulating packets to be outputted from the output-side interface and a second queue for accumulating packets addressed to CPU, and accumulate the packets in a buffer, the scheduler managing the order of outputting the packets accumulated in the queues of the buffer to output the packets accumulated in the first queue to the output-side interface and output the packets accumulated in the second queue to the first storage device.
According to another aspect of the present invention, a packet switch comprising:
at least one ingress-side physical layer controller connected to a physical layer which is an input side of the packets;
at least one ingress-side line interface device connected to the ingress-side physical layer controller;
a routing switch connected to the ingress-side line interface device;
at least one egress-side line interface device connected to the routing switch; and
at least one egress-side physical layer controller having one side connected to the egress-side line interface device and the other side connected to a physical layer which is the output side of the packets,
wherein each line interface device of the ingress-side line interface device and the egress-side line interface device comprises;
an input-side interface supplied with the packets;
an output-side interface outputting the packets;
a buffer supplied with packets outputted from the input-side interface and accumulating the packets classified at least into a first queue for accumulating packets to be outputted from the output-side interface and a second queue for accumulating packets addressed to CPU;
a first storage device configured to temporarily store packets outputted from the buffer toward the CPU and be accessed by the CPU when necessary; and
a scheduler configured to manage the order of outputting the packets accumulated in the queues of the buffer to output the packets accumulated in the first queue to the output-side interface and output the packets accumulated in the second queue to the first storage device.
According to a further aspect of the present invention, a line interface integrated circuit having a physical layer interface connected to a physical layer controller to input and output packets, and a switch interface connected to a routing switch to output and input packets, comprising:
first and second storage devices configured to temporarily store packets toward CPU and being accessed by the CPU when necessary;
an ingress-side scheduler configured to classify the packets outputted from the physical layer interface at least into a first queue for accumulating packets to be outputted from the switch interface and a second queue for accumulating packets addressed to the CPU, and accumulate the packets in an ingress-side buffer, the ingress-side scheduler managing the order of outputting the packets accumulated in the queues of the ingress-side buffer to output the packets accumulated in the first queue to the switch interface and output the packets accumulated in the second queue to the first storage device; and
an egress-side scheduler configured to classify the packets outputted from the switch interface at least into a third queue for accumulating packets to be outputted from the physical layer interface and a fourth queue for accumulating packets addressed to the CPU, and accumulate the packets in an egress-side buffer, the egress-side scheduler managing the order of outputting the packets accumulated in the queues of the egress-side buffer to output the packets accumulated in the third queue to the physical layer interface and output the packets accumulated in the fourth queue to the second storage device.
According to a still further aspect of the present invention, a packet switch comprising:
at least one physical layer controller connected to a physical layer;
at least one line interface device connected to the physical layer controller; and
a routing switch connected to the line interface device
wherein the line interface device comprises:
a physical layer interface connected to the physical layer controller to input and output packets;
a switch interface connected to the routing switch to output and input packets;
an ingress-side buffer supplied with the packets outputted from the physical layer interface, and accumulating the packets classified at least into a first queue for accumulating packets to be outputted from the switch interface and a second queue for accumulating packets addressed to CPU;
a first storage device configured to temporarily store packets outputted from the ingress-side buffer toward the CPU and be accessed by the CPU when necessary;
an ingress-side scheduler configured to manage the order of outputting the packets accumulated in the queues of the ingress-side buffer to output the packets accumulated in the first queue to the switch interface and output the packets accumulated in the second queue to the first storage device;
an egress-side buffer supplied with the packets outputted from the switch interface, and accumulating the packets classified at least into a third queue for accumulating packets to be outputted from the physical layer interface and a fourth queue for accumulating packets addressed to the CPU;
a second storage device configured to temporarily store packets outputted from the egress-side buffer toward the CPU and be accessed by the CPU when necessary; and
an egress-side scheduler configured to manage the order of outputting the packets accumulated in the queues of the egress-side buffer to output the packets accumulated in the third queue to the physical layer interface and output the packets accumulated in the fourth queue to the second storage device.